DocumentCode
156564
Title
Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding
Author
Chang Hao ; Liang Huaguo ; Li Yang ; Ouyang Yiming
Author_Institution
Sch. of Comput. & Inf., Hefei Univ. of Technol., Hefei, China
fYear
2014
fDate
28-30 April 2014
Firstpage
1
Lastpage
4
Abstract
One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond order to screen out the failed component as early as possible. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D-SICs considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. Experimental results demonstrate that the proposed rearranged stacking method is only a half of the sequential stacking in terms of failed area ratio (FAR).
Keywords
integrated circuit bonding; integrated circuit modelling; integrated circuit testing; integrated circuit yield; probability; three-dimensional integrated circuits; 2D test flow; 3D stacked integrated circuits; 3D test flow; FAR; bonding arrangement; cost model; die yield; failed area ratio; failure rate; midbond test; optimized stacking order; probability; rearranged stacking method; sequential stacking; stacking yield; yield model; Bonding; Educational institutions; Redundancy; Stacking; Testing; Three-dimensional displays; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/VLSI-DAT.2014.6834877
Filename
6834877
Link To Document