Cycle-slip-detector-aided iterative timing recovery algorithm

Summary form only given. Recent research on capacity approaching codes, i.e., low density parity check (LDPC) codes and turbo codes, assumes perfect timing recovery systems. Conventional timing recovery devices tend to experience cycle-slips at low signal-to-noise ratios (SNRs). In our previous work, we developed a cycle-slip detector (CSD) for AWGN channels using the decoder soft information. In this paper, we generalize the method and develop the CSD for channels with intersymbol interference. We investigate the PR4 (1-D/sup 2/) channel with a rate 4/5 LDPC code. The channel experiences a slowly time-varying phase drift. We use the Mueller and Muller (M&M) synchronizer to track the phase drift. For i.i.d. equally likely binary symbols, the soft information is the symbol a posteriori probability (APP). Both the symbol APPs and the preliminary decisions for the timing recovery algorithm are provided by a forward-only implementation of the BCJR algorithm, with a survival memory length of 6. This paper further investigates an iterative timing recovery scheme with the aid of the CSD.