• DocumentCode
    1566035
  • Title

    Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor

  • Author

    Mehdizadeh, Nima ; Shokrolah-Shirazi, Mohammad ; Miremadi, Seyed Ghassem

  • Author_Institution
    Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran
  • fYear
    2008
  • Firstpage
    648
  • Lastpage
    652
  • Abstract
    This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core described at the RTL model. A comparison of the effects of faults on the various parts of the CPU including the pipeline´s registers, the CPU component such as the register file, the control unit, and the ALU, and the data and address buses is done. It is shown that about 30%, 40% and 27% of injected faults terminated in address, data, and control errors respectively. About 28% of all injected faults resulted in failures.
  • Keywords
    fault tolerance; microprocessor chips; pipeline processing; reduced instruction set computing; CPU component; RTL model; fault tolerance; openRISC 1200 microprocessor; pipeline register; reduced instruction set computing; transient fault effect analysis; Analytical models; Cache memory; Computer architecture; Digital systems; Fault tolerance; Microprocessors; Reduced instruction set computing; Registers; Single event upset; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Availability, Reliability and Security, 2008. ARES 08. Third International Conference on
  • Conference_Location
    Barcelona
  • Print_ISBN
    978-0-7695-3102-1
  • Type

    conf

  • DOI
    10.1109/ARES.2008.55
  • Filename
    4529404