A new approach of a self-timed bit-serial synchronous pipeline architecture

Power consumption, area minimization as well as signal delay and reconfiguration with respect to rapid system prototyping make increasing demands on chip design. While design space can be reduced by bit-serial operators, long control lines in synchronous bit-serial architecture usually affect the performance of the circuit. This paper presents a new synchronous, fully reconfigurable self-timed bit-serial and fully interlocked pipeline architecture. Through a one-hot implementation of the central control engine, we realize the local control of the operators. Furthermore, we developed a specialized routing component that allows the reconfiguration of the implementation w.r.t. rapid system prototyping. This realization of the developed architectures provides the freedom of a rapid system prototyping of a given problem. To our knowledge, this is the second paper detailing the implementation of a fully interlocked synchronous architecture after the one by Jacobson et al. (2002) and the first which does not rely on gated clocks to realize the local control of the operators. We prove the usefulness of our architecture by an example implementation of a given problem on a Xilinx FPGA. The architecture is optimized for the use in embedded systems to control mechatronic systems, but can also be employed in other fields of application.