Title :
A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits
Author :
Rong-Zhou Kuo ; Hao-Chiao Hong
Author_Institution :
Inst. of Electr. Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; bootstrap circuits; low-power electronics; CMOS; ERBW; Nyquist bandwidth; bootstrapped switches; building block; effective resolution bandwidth; frequency 250 Hz; low-power applications; low-voltage amplifier; power 17 nW; rail-to-rail SAR ADC; rail-to-rail signal swing; signal-to-noise-and-distortion ratio; size 0.18 mum; successive approximation register analog-to-digital converter; voltage 0.5 V; Approximation methods; Bandwidth; CMOS integrated circuits; Capacitors; Clocks; MOSFET;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2014.6834905
