Title :
A 22.4 fJ/conversion 0.7V 1.6μW 10-bit successive approximation ADC
Author :
Meng-Lieh Sheu ; Te-Hsiang Liu ; Lin-Jie Tsao
Author_Institution :
Dept. of Electron. Eng., Nat. Chi-Nan Univ., Nantou Hsien, Taiwan
Abstract :
A 10-bit successive approximation ADC for low voltage and low power applications is proposed in this paper. The chip operating voltage is 0.7 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayered sandwich capacitor array is used in the digital to analog converter employed in the ADC to reduce the overall capacitance value and power consumption effectively. The proposed ADC is implemented in 0.18 μm CMOS technology with core active area of 201 μm × 180 μm. From the measurement results at 0.7 V supply voltage, 2.4 MHz operating frequency, 200 kS/s sampling rate, and 1 kHz rail-to-rail swing input, an SNDR of 52.95 dB is achieved with 1.624 μW power consumption. The FOM is 22.4 fJ per conversion step. And its ERBW is up to Nyquist rate.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; digital-analogue conversion; low-power electronics; CMOS technology; analog-to-digital converters; binary-weighted multilayered sandwich capacitor array; digital-to-analog converter; frequency 2.4 MHz; power 1.624 muW; size 0.18 mum; size 180 mum; size 201 mum; successive approximation ADC; voltage 0.7 V; word length 10 bit; Approximation methods; Capacitance; Capacitors; Frequency measurement; Low voltage; Power demand; Semiconductor device measurement;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2014.6834907
