Zero-skew driven for RLC clock tree construction in SoC

In this paper, we observe that the clock tree in a SoC is unbalanced in nature and derive that a RC clock tree has the characteristic of exact zero-skew upward propagation but not for an unbalanced RLC clock tree. Illustrated inductions are helped to prove the observation. We develop a zero-skew driven algorithm for constructing a RLC clock tree to minimize the skew. More examples and benchmarks are evaluated. The difference in skew ratio and the tolerance in path delay compared with HSPICE are 1.15409% and 10.645%, respectively, on average.