Next generation environment for extremely fast test pattern generation

Author

Pulini, Gabriele ; Hamacher, Stefan

Author_Institution

Mentor Graphics Europe, UK

fYear

1993

Firstpage

422

Lastpage

425

Abstract

The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well

Keywords

application specific integrated circuits; automatic testing; circuit CAD; design for testability; integrated circuit design; integrated circuit testing; ASIC; ATPG; IC design; design-for-test; full-scan designs; partial-scan automatic test pattern generator; scan-test tools; sequential ATPG; target design flow; test pattern generation; test vector creation; Application specific integrated circuits; Automatic test pattern generation; Costs; Design for testability; Electronic design automation and methodology; Electronic equipment testing; Integrated circuit testing; Registers; Sequential analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Conference_Location

Hamburg

Print_ISBN

0-8186-4350-1

Type

conf

DOI

10.1109/EURDAC.1993.410671

Filename

410671