FPGA prototype design of Network on Chips

Multi-core technology has become a trend in high performance System on Chip (SoC) design. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture for its extensibility and power efficiency. This paper proposed crossbar NoC architecture and its FPGA prototype design, and the major contribution lies in the following aspects. Fist, a NoC with both shared variable and message passing programming models is proposed. The shared variable method uses previously designed hierarchy bus and the message passing model uses the full connect crossbar. Second, a 4-core NoC FPGA prototype is implemented on the Altera FPGA device. Resource utilization is analyzed between the crossbar NoC and the hierarchy bus components. Experimental results showed the resource utilization of crossbar NoC modules are very small with 2.85% in combinational logic and 3.69% in sequential logic.