Pareto optimization of analog circuits considering variability

Until recently, analog sizing decided a-priori by weight assignment the trade-off between competing design objectives. Nowadays, architectural design requires the knowledge of all possible optimal trade-offs of a building block. Methods for Pareto optimization provide the set of all optimal trade-offs, the so-called Pareto front. The next generation of analog Pareto optimization tools has to additionally consider the manufacturing variations. This paper will describe an approach to this challenging problem. It is based on the computation of the worst-case performance values on discrete sets of Pareto points that cover the Pareto front.