DocumentCode
1567424
Title
Verification of Split&Shift techniques for CNN hardware reduction
Author
Fernández-Garcìa, N.A. ; Albó-Canals, Jordi ; Brea, Victor M. ; Riera-Baburés, Jordi ; Cabello, Diego ; Vilasìs-Cardona, Xavier
Author_Institution
Dept. de Electron. e Comput., Univ. de Santiago de Compostela, Santiago de Compostela
fYear
2007
Firstpage
88
Lastpage
91
Abstract
The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.
Keywords
field programmable gate arrays; nonlinear network analysis; FPGA platform; area saving technique; cellular nonlinear networks; hardware implementation; split&shift techniques; Cellular networks; Cellular neural networks; Circuit synthesis; Computer architecture; Computer networks; Emulation; Field programmable gate arrays; Hardware; Network-on-a-chip; Pixel;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Conference_Location
Seville
Print_ISBN
978-1-4244-1341-6
Electronic_ISBN
978-1-4244-1342-3
Type
conf
DOI
10.1109/ECCTD.2007.4529543
Filename
4529543
Link To Document