Title :
On the modeling and testing of VHDL behavioral descriptions of sequential circuits
Author :
Pla, Véronique ; Santucci, Jean-Francois ; Giambiasi, Norbert
Author_Institution :
LERI, Nimes, France
Abstract :
A new automatic test generation principle based on a formal modeling of VHDL behavioral descriptions is proposed. Using to the finite state machine representation and a formalism close to that of Petri nets, the authors define two models which represent all the concepts associated with a VHDL description. They then propose a generation principle which uses both forward and backward time processing
Keywords :
Petri nets; finite state machines; hardware description languages; logic CAD; logic design; logic testing; sequential circuits; Petri nets; VHDL behavioral descriptions; automatic test generation; backward time processing; finite state machine representation; formal modeling; forward time processing; sequential circuits; Automata; Automatic test pattern generation; Circuit faults; Circuit testing; Petri nets; Programmable logic arrays; Sequential analysis; Sequential circuits; Signal processing; Test pattern generators;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410674
