Thermometer-to-binary decoders for flash analog-to-digital converters

Author

Säll, Erik ; Vesterbacka, Mark

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Linkoping

fYear

2007

Firstpage

240

Lastpage

243

Abstract

Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.

Keywords

CMOS integrated circuits; analogue-digital conversion; decoding; error correction; multiplexing equipment; read-only storage; silicon-on-insulator; 4-level folded Wallace-tree; CMOS SOI technology; ROM decoder; energy consumption; error correction; flash analog-to-digital converters; high-speed flash ADC; multiplexer-based decoder; thermometer-to-binary decoders; Analog-digital conversion; CMOS technology; Circuits; Decoding; Energy consumption; Error correction; Propagation delay; Read only memory; Sampling methods; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on

Conference_Location

Seville

Print_ISBN

978-1-4244-1341-6

Electronic_ISBN

978-1-4244-1342-3

Type

conf

DOI

10.1109/ECCTD.2007.4529581

Filename

4529581