Title :
Top-down modeling of RISC processors in VHDL
Author :
Juan, Hsiao-Ping ; Holmes, Nancy D. ; Bakshi, Smita ; Gajski, Daniel D.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
The authors present a high-level design modeling methodology with three modeling levels: a specification level, an interface level, and a functional level. They demonstrate the methodology on a RISC processor design. All models have been implemented in VHDL and simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results demonstrate the feasibility and usefulness of the methodology
Keywords :
hardware description languages; high level synthesis; logic design; microprocessor chips; reduced instruction set computing; 32-bit processor; RISC processors; SPARC 1 workstation; VHDL; ZYCAD VHDL simulator; feasibility; functional level; high-level design modeling; interface level; microprocessor; specification level; version 1.0a; Computer science; Costs; Design methodology; Documentation; Emulation; Process design; Protocols; Reduced instruction set computing; Testing; Workstations;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410676
