An FPGA implementation Of 2-D CNN gabor-type filter

Author

Saatci, Ertugrul ; Cesur, Evren ; Tavsanoglu, Vedat ; Kale, Izzet

Author_Institution

Dept. of Comput. Eng., Istanbul Kultur Univ., Istanbul

fYear

2007

Firstpage

280

Lastpage

283

Abstract

A field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 times 60 can be processed without using any external RAM only with the block RAM.

Keywords

Gabor filters; approximation theory; field programmable gate arrays; 2D CNN Gabor-type filter; FPGA; Xilinx Spartan XC3S400 device; cell-state equation; field programmable gate array; forward Euler approximation; Artificial intelligence; Bismuth; Cellular neural networks; Equations; Feedforward systems; Field programmable gate arrays; Gabor filters; Nonlinear filters; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on

Conference_Location

Seville

Print_ISBN

978-1-4244-1341-6

Electronic_ISBN

978-1-4244-1342-3

Type

conf

DOI

10.1109/ECCTD.2007.4529591

Filename

4529591

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1567966