A practice of ESL verification methodology from SystemC to FPGA - using EPC Class-1 Generation-2 RFID tag design as an example

This paper presents the first published industrial practice (to the best of our knowledge) to reuse high-level/C++ system simulation model through OSCI TLM 2.0 Library to verify its corresponding RTL implementation in FPGA. ESL verification methodology is employed in the design regression of EPC C1Gen2 RFID tag. Around 200 times speedup is observed using ESL over conventional RTL simulation in regression runs (after logic bug fixes). This clearly shows ESL verification is a successful candidate to reuse high-level test harness for IC functional verification, especially in today´s increasingly complex IC design world. On top of the successful use of the ESL functional verification flow on the design, we also show the infrastructure to use SystemC Verification Library (SCV) for formal verification. The functional and formal verification combined is thus the proposed ESL verification methodology.