A high-speed hardware implementation of the Hermes8-128 stream cipher

An efficient high-speed hardware implementation of the Hermes8-128 stream cipher is presented in this paper. Hermes8-128 is proposed for hardware based implementations in the eSTREAM project. Two FPGA devices are used for the hardware implementations. Especially, the XILINX (Spartan-2) 2S100-6 and (VIRTEX-4) 4VFX12-11 are used. A maximum throughput of 56.5 Mbps can be achieved with a clock frequency of 49 MHz with a XC2S100-6 device, while a throughput of 361 Mbps at 313 MHz is achieved with the 4VFX12-11 device. Since now only one previous reported Hermes8-128 hardware implementation exists, a comparison with the proposed one is given.