Arithmetic and architectural design to reduce leakage in nano-scale digital circuits

Most of the power consumption, in standard CMOS, has in the past been related to the dynamic activities. However, in nano-meter scale technologies the static power, i.e. leakage, is an important contribution to the total power consumption. This paper discusses static and dynamic power reduction methodologies on architectural and arithmetical level. Techniques to reduce the static power consumption in digital applications for nano-scale CMOS technologies are addressed. A 79% arithmetic reduction of the static power consumption is indicated, by using serial arithmetic instead of bit-parallel. Digit-serial arithmetic shows power reductions between 32 and 67%, depending on the digit size and technology.