Analysis of multi-process VHDL specifications with a Petri net model

Author

Müller, J. ; Kramer, H.

Author_Institution

Forschungszentrum Inf., Karlsruhe, Germany

fYear

1993

Firstpage

474

Lastpage

479

Abstract

A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain

Keywords

Markov processes; Petri nets; formal specification; hardware description languages; high level synthesis; optimisation; probability; synchronisation; Markov chain; Petri net model; access conflicts; global data signals; multi-process VHDL specifications; probabilities; reduced case graph; state transition graph; stationary distribution; synchronization; system-level synthesis; Circuit synthesis; Clocks; Design automation; Optimization methods; Probability; Signal analysis; Signal processing; Signal synthesis; Synchronization; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Conference_Location

Hamburg

Print_ISBN

0-8186-4350-1

Type

conf

DOI

10.1109/EURDAC.1993.410679

Filename

410679