Implementation of hierarchical design for testability methodology

Author

Yansheng, Zhang ; Jianhui, Chen ; Jianhui, Jin

Author_Institution

Mech. Eng. Coll., Shijiazhuang, China

fYear

2009

Abstract

A comprehensive test strategy initiated as early into the design cycle as possible can yield significant improvement in test coverage, faster fault diagnosis, lowered test and development costs, shorter system development time, and faster time to market. One means of improving the testability of systems is to adopt a structured, hierarchical design methodology, and a corresponding hierarchical test methodology. This paper would introduce the implementation of hierarchical design for testability (DFT) methodology from three ways: hierarchical structure, hierarchical test buses based on MIL-STD-1553B, IEEE 1149.5, and IEEE 1149.1, and concurrent test engineering.

Keywords

concurrent engineering; design; electronic equipment testing; DFT methodology; concurrent test engineering.; design for testability; hierarchical design; testability methodology; Built-in self-test; Circuit testing; Consumer electronics; Costs; Design engineering; Design for testability; Electronic equipment testing; Integrated circuit interconnections; Logic testing; System testing; DFT; concurrent test engineering; hierarchical design; testability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Measurement & Instruments, 2009. ICEMI '09. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3863-1

Electronic_ISBN

978-1-4244-3864-8

Type

conf

DOI

10.1109/ICEMI.2009.5274852

Filename

5274852