Title :
Design time body bias selection for parametric yield improvement
Author :
Zhuo, Cheng ; Chang, Yung-Hsu ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
EECS Dept., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
Circuits designed in aggressively scaled technologies face both stringent power constraints and increased process variability. Achieving high parametric yield is a key design objective, but is complicated by the correlation between power and performance. This paper proposes a novel design time body bias selection framework for parametric yield optimization while reducing testing costs. The framework considers both inter- and intra-die variations as well as power-performance correlations. This approach uses a feature extraction technique to explore the underlying similarity between the gates for effective clustering. Once the gates are clustered, a Gaussian quadrature based model is applied for fast yield analysis and optimization. This work also introduces an incremental method for statistical power computation to further reduce the optimization complexity. The proposed framework improves parametric yield from 39% to 80% on average for 11 benchmark circuits while runtime is linear with circuit size and on the order of minutes for designs with up to 15 K gates.
Keywords :
feature extraction; integrated circuit design; integrated circuit manufacture; Gaussian quadrature; benchmark circuits; design time body bias selection; fast yield analysis; feature extraction technique; parametric yield improvement; power constraints; power-performance correlations; Chip scale packaging; Circuit optimization; Circuit testing; Cost function; Delay; Design optimization; Integrated circuit yield; Manufacturing; Optimization methods; Voltage;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419802