Title :
50% PAE 20-mA quiescent current W-CDMA power amplifier with on-chip dynamic-gain linearizer
Author :
Aoki, Yuuichi ; Yamanouchi, Shingo ; Kunihiro, Kazuaki ; Miyazaki, Takashi ; Hirayama, Tomohisa ; Hida, Hikaru
Author_Institution :
Res. Lab. of Syst. Devices, NEC Corp., Kawasaki, Japan
Abstract :
This paper explains a power-effective linearization technique for power amplifiers (PAs) having gain-expansion characteristics. A new on-chip dynamic-gain-deviation cancellation circuit improves the adjacent-channel-leakage-power ratio (ACLR) for a W-CDMA signal by 11 dB. At a supply of 3.5 V and an output power of 26.9 dBm, a fabricated PA with a quiescent current (Iq) of 19 mA exhibited a power-added efficiency of 50%, a gain of 26 dB, and an ACLR of -40 dBc. Furthermore, when we applied this technique to a PA with Iq of only 10-mA, this PA also satisfied the W-CDMA criteria.
Keywords :
broadband networks; code division multiple access; linearisation techniques; mobile radio; power amplifiers; radiofrequency amplifiers; 10 mA; 19 mA; 20 mA; 26 dB; 3.5 V; 50 percent; W-CDMA power amplifier; adjacent-channel-leakage-power ratio; dynamic-gain-deviation cancellation circuit; on-chip dynamic-gain linearizer; power-effective linearization technique; quiescent current; Broadband amplifiers; Circuits; Gain; High power amplifiers; Linearization techniques; Multiaccess communication; Power amplifiers; Power generation; Switches; System-on-a-chip;
Conference_Titel :
Radio and Wireless Symposium, 2006 IEEE
Print_ISBN :
0-7803-9412-7
DOI :
10.1109/RWS.2006.1615142
