DocumentCode :
15689
Title :
Super-Altro 16: A Front-End System on Chip for DSP Based Readout of Gaseous Detectors
Author :
Aspell, P. ; De Gaspari, M. ; Franca, H. ; Garcia, E.G. ; Musa, L.
Author_Institution :
CERN, Geneva, Switzerland
Volume :
60
Issue :
2
fYear :
2013
fDate :
Apr-13
Firstpage :
1289
Lastpage :
1295
Abstract :
This paper presents the architecture, design and test results of an ASIC specifically designed for the readout of gaseous detectors. The primary application is the readout of the Linear Collider Time Projection Chamber. The small area available (4 mm2 /channel) requires an innovative design, where sensitive analog components and massive digital functionalities are integrated on the same chip. Moreover, shut down (power pulsing) features are necessary in order to reduce the power consumption. The Super-Altro is a 16-channel demonstrator ASIC involving analog and digital signal processing. Each channel contains a low noise Pre-Amplifier and Shaping Amplifier (PASA), a pipeline ADC, and a Digital Signal Processor (DSP). The PASA is programmable in terms of gain and shaping time and can operate with both positive and negative polarities of input charge. The 10-bit ADC samples the output of the PASA at a frequency up to 40 MHz before providing the digitized signal to the DSP which performs baseline subtraction, signal conditioning, drift correction and zero suppression. The chip has been fabricated in a 130 nm CMOS technology. Test measurements show correct functionality of the full system, and demonstrate that, using appropriate design techniques, the extensive digital circuitries produce little or no degradation of analog performance (particularly noise).
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; application specific integrated circuits; digital readout; digital signal processing chips; integrated circuit design; integrated circuit testing; ionisation chambers; nuclear electronics; power consumption; preamplifiers; signal conditioning circuits; time projection chambers; 10-bit ADC samples; 16-channel demonstrator ASIC; CMOS technology; DSP based readout; Linear Collider Time Projection Chamber; Super-Altro; analog performance; analog signal processing; baseline subtraction; design techniques; digital functionalities; digital signal processing; digital signal processor; drift correction; extensive digital circuitries; front-end system; gaseous detectors; input charge; low noise PreAmplifier and Shaping Amplifier; pipeline ADC; power consumption; power pulsing; sensitive analog components; shut down features; signal conditioning; size 130 nm; test measurements; Clocks; Detectors; Digital signal processing; Noise; Pipelines; Resistors; System-on-chip; Front-end; gaseous detectors; linear collider TPC; mixed analog digital integrated circuits; system-on-chip;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2013.2250305
Filename :
6496307
Link To Document :
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