Limited intermediate buffer switch modules and their interconnection networks for B-ISDN

Gupta et al. (1991) presented an analysis of a limited intermediate buffer (LIB) switch consisting of input buffers and a limited amount of buffers in the switch fabric, where contention for the output ports occurs. A novel scheduling scheme based on head of line blocking was proposed, which improved the performance significantly. For uniform random traffic, a 16×16 LIB switch had an achievable throughput equal to 87.5%. The authors examine the switch performance under two delay dependent priority classes and show that the achievable throughput can be increased to 91%. To build large-size switching systems, a multistage interconnection network is proposed, which meets the demands of large-scale asynchronous transfer mode (ATM) switch design, such as (1) modularity, (2) relaxed synchronization, (3) guaranteed high performance without requiring internal speedup, and (4) maintaining packet sequence integrity. The simulation results of three-stage interconnection networks prove the efficacy of the LIB switch architecture and the proposed scheduling scheme