A fault-tolerant switching architecture for ATM networks

The author proposes a self-routing fault-tolerant switching network for asynchronous transfer mode (ATM) systems. The network has many subswitches to give a higher fault tolerance than the conventional multistage interconnection network, which only has a unique path. The subswitches provide many alternative paths and allow the network to tolerate multiple faults. The extra paths can also be used to route cells when internal cell contention occurs in switching elements. Quantitative analysis shows a significant higher fault tolerance than previously presented fault-tolerant networks. A performance analysis by simulation showed that the proposed network had a high maximum throughput. The level of throughput was maintained with acceptable cell delay even though the number of faulty components increased