DocumentCode
1569012
Title
SOC for car navigation system with a 55.3GOPS image recognition engine
Author
Hamasaki, Hiroyuki ; Hoshi, Yasuhiko ; Nakamura, Atsushi ; Yamamoto, Akihiro ; Kido, Hideaki ; Muramatsu, Shoji
Author_Institution
Renesas Technol. Corp., Kodaira, Japan
fYear
2010
Firstpage
464
Lastpage
465
Abstract
This paper introduces the system on a chip (SOC) equipped with dual RISC processors, an image recognition engine operating with up to 55.3 GOPS, multiple accelerators and peripherals for car navigation systems. The SoC has high performance with respect to image recognition applications which are installed in advanced vehicles as well as navigation function such as graphics operating at the same time. Furthermore we have developed the SoC in order to meet automotive specifications including cost and size. We report practical application which is for the pedestrian detection to demonstrate our SoC capability. We accelerate the application with combination of the RISC processor and image recognition engine.
Keywords
image recognition; reduced instruction set computing; system-on-chip; traffic engineering computing; 55.3 GOPS image recognition engine; car navigation system; dual RISC processors; multiple accelerators; pedestrian detection; system on a chip; Acceleration; Automotive engineering; Costs; Engines; Graphics; Image recognition; Intelligent vehicles; Navigation; Reduced instruction set computing; System-on-a-chip; SoC; car navigation systems; image recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location
Taipei
Print_ISBN
978-1-4244-5765-6
Electronic_ISBN
978-1-4244-5767-0
Type
conf
DOI
10.1109/ASPDAC.2010.5419837
Filename
5419837
Link To Document