A novel CMOS integrated smart antenna transceiver

Author

Ahmadi, M.R.N. ; Chen, Lisa Yun ; Fayyaz, Nader ; Safavi-Naeini, Safieddin ; Banbury, David R.

Author_Institution

Dept. of Electr. Eng., Waterloo Univ., Ont., Canada

fYear

2006

Firstpage

299

Lastpage

302

Abstract

A novel CMOS 5.5/2.4 GHz dual-band smart antenna architecture for WLAN 802.11a/b/g is presented. The front-end chip has a super-heterodyne architecture with an intermediate frequency (IF) of 1.25-1.75 GHz. A novel integrated phase shifter in this chip realizes a variable phase shift, ranging from 0° to 400°, in each local oscillator (LO) path. The front-end chip reduces undesirable RF interference by up to 40 dB, and improves the signal to noise level by up to 3 dB. The chip, fabricated in 0.18 μm 60 GHz CMOS technology, is 2 mm × 2 mm in size. It has an overall power consumption of 100 mW with an acceptable supply voltage range of 1.5 V to 1.8 V.

Keywords

CMOS analogue integrated circuits; MMIC oscillators; MMIC phase shifters; UHF antennas; UHF oscillators; UHF phase shifters; adaptive antenna arrays; microwave antennas; transceivers; 0.18 mum; 1.25 to 1.75 GHz; 1.5 to 1.8 V; 100 mW; 2.4 GHz; 5.5 GHz; CMOS; The front-end chip; WLAN 802.11; dual-band smart antenna architecture; integrated phase shifter; local oscillator; smart antenna transceiver; CMOS technology; Dual band; Electromagnetic interference; Frequency; Local oscillators; Noise level; Phase shifters; RF signals; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Symposium, 2006 IEEE

Print_ISBN

0-7803-9412-7

Type

conf

DOI

10.1109/RWS.2006.1615154

Filename

1615154