Universal-coding-rate scarce-state-transition Viterbi decoder

The authors propose a universal-coding-rate scarce-state-transition Viterbi decoder that permits the realization of a high-speed high-coding-rate one-chip forward error correction CMOS LSIC. To reduce the power consumption of high-coding-rate Viterbi decoders, the proposed decoder expands the scarce-state-transition (SST) Viterbi decoding scheme from a coding rate of one-half to any higher coding rate. To employ the SST Viterbi decoding scheme for high-coding-rate convolutional codes, a universal predecoding scheme for convolutional codes is introduced. Computer simulations showed a drastic reduction in CMOS gate on-off switching. A low-power-consumption path memory is proposed to reduce the power consumption. A pilot chip was fabricated and its total power consumption was reduced by 27% for rate three-fourths coding rate Viterbi decoding