DocumentCode
1569399
Title
A high-speed frequency acquisition PLL using phase frequency detector with variable gain
Author
Yau, Jerry ; Tu, Steve Hung-Lung
Author_Institution
Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan
fYear
2010
Firstpage
101
Lastpage
104
Abstract
Conventional phase-locked loops (PLL) with a tri-state phase frequency detector (PFD) and a charge pump (CP) typically suffer long locking time in video applications due to low reference frequency (30K Hz~150kHz). In this paper, we propose a novel multi-state phase frequency detector with variable gain which can efficiently reduce the locking time. The post-layout simulation results indicate that the locking time of the PLL using the proposed novel multi-state PFD can be reduced about 49% compared with conventional PFDs.
Keywords
phase locked loops; charge pump; frequency 30 kHz to 150 kHz; frequency acquisition phase-locked loop; multistate phase frequency detector; post-layout simulation; tri-state phase frequency detector; variable gain; video application; Charge pumps; Filters; Gain; Phase detection; Phase frequency detector; Phase locked loops; Signal generators; Space vector pulse width modulation; Switches; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location
Seattle, WA
ISSN
1548-3746
Print_ISBN
978-1-4244-7771-5
Type
conf
DOI
10.1109/MWSCAS.2010.5548571
Filename
5548571
Link To Document