An efficient parallel structure for ΣΔ modulators for use in high speed switching power amplifiers

Switching amplifiers using sigma-delta modulators have proven to be highly efficient but require high switching speeds. Implementing complete digital systems at the switching speed has prevented their use in higher speed applications. In this paper we propose a methodology for the parallelisation of sigma-delta modulators allowing for the partition of the switching amplifier into a low-speed and high speed sections. This will enable switching amplifiers to be used effectively at higher frequencies, and specifically for wireless applications.