Optimized BIST for embedded dual-port RAMs

Author

Karunaratne, Maddu ; Oomman, Bejoy

Author_Institution

Univ. of Pittsburgh, Pittsburgh, PA, USA

fYear

2010

Firstpage

125

Lastpage

128

Abstract

This paper describes new optimal test pattern generation algorithms for embedded dual-port random access memories (DPRAMs) which have two independent read-write ports. They are widely used in networking and communications integrated circuits (IC). The widely available standard extensions of March algorithms for DPRAMs are not guaranteed to detect certain inter-port coupling faults which are explained in here. This paper describes a novel optimal test method using March test algorithms that also cover such faults efficiently.

Keywords

automatic test pattern generation; built-in self test; embedded systems; fault diagnosis; random-access storage; DPRAM; March algorithms; March test algorithms; embedded dual-port RAM; embedded dual-port random access memory; integrated circuits; inter-port coupling faults; optimal test method; optimal test pattern generation algorithms; optimized BIST; read-write ports; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic testing; Random access memory; Read-write memory; Silicon; BIST; Dual-port; Fault model; March Algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Conference_Location

Seattle, WA

ISSN

1548-3746

Print_ISBN

978-1-4244-7771-5

Type

conf

DOI

10.1109/MWSCAS.2010.5548574

Filename

5548574