Power and area efficient 5T-SRAM with improved performance for low-power SoC in 65nm CMOS

This paper addresses performance and reliability issues in a 5T SRAM cell, and introduces a low power, reliable and high performance design in 65nm technology, which can be used as cache memory in processors and in low-power portable devices. The proposed SRAM cell features ~13% area reduction compared to a typical 6T cell. In addition, it features a biasing ground line, VSSM, which is charged by channel leakage current from memory cells in standby, and is used to pre-charge a single bit-line and bias the negative supply voltage of each memory cell to suppress standby leakage power. A major standby power reduction is gained compared to conventional 5T and 6T designs and up to ~30% compared to previous low-power 6T designs. The proposed design has read and static noises margins, as well as write `0´ and read performance that are comparable to typical 6T designs. Write `1´ is slower by ~11-31% depending on design choices and can be improved with minor cost of area and power.