Title :
Integrated read assist-sense amplifier scheme for high performance embedded SRAMs
Author :
Shakir, Tahseen ; Rennie, David ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
Abstract :
Embedded memories have become a dominant block in modern SOCs and often constitute more than half the die area. Sense amplifiers are crucial circuits in memories as they are largely responsible for the read operation. The scaling of CMOS technology deep into the sub-micron range has created numerous challenges for SRAMs; notably in that conventional sense amplifier architectures suffer from mismatch and process variability. This paper presents a novel sensing schemes featuring a read assist circuit that enhances the SRAM cell operation and robustness. Schematic and post layout simulation results show a 60% speed improvement and 62% power saving as compared to conventional sensing schemes.
Keywords :
CMOS integrated circuits; SRAM chips; circuit simulation; embedded systems; integrated circuit layout; system-on-chip; CMOS technology; SOC; SRAM cell operation; embedded memory; high performance embedded SRAM; integrated read assist-sense amplifier scheme; post layout simulation; process variability; read assist circuit; sense amplifier architectures; sense amplifiers; submicron range; CMOS technology; Circuit simulation; Differential amplifiers; Inverters; Latches; Operational amplifiers; Random access memory; Read-write memory; Robustness; Voltage;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548581
