A low voltage CMOS analog multiplier with high linearity

Author

Miremadi, Amir H. ; Ayatollahi, Ahmad ; Abrishamifar, Adib ; Siadatan, Alireza

Author_Institution

Dept. of Electr. Eng., Islamic Azad Univ., Tehran, Iran

fYear

2009

Firstpage

257

Lastpage

262

Abstract

This paper presents a single low-voltage CMOS analog multiplier with high-linearity, low total harmonic distortion and low-power consumption. It consists of four voltage adders, four nullors and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 1 V supply voltage, the circuit has smaller than 0.65% linearity error and 0.36% THD under the maximum-scale input 400 mVp-p at both inputs. The quiescent power consumption is 120 muW and the -3 dB bandwidth is 30 MHz.

Keywords

CMOS analogue integrated circuits; SPICE; active networks; adders; analogue multipliers; harmonic distortion; low-power electronics; HSPICE simulation; bandwidth 30 MHz; linearity error; low voltage CMOS analog multiplier; low-power consumption; nullors; power 120 muW; total harmonic distortion; voltage 1 V; voltage adders; Adders; Bipolar integrated circuits; CMOS technology; Circuit simulation; Energy consumption; Frequency; Linearity; Low voltage; Power supplies; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Conference_Location

Antalya

Print_ISBN

978-1-4244-3896-9

Electronic_ISBN

978-1-4244-3896-9

Type

conf

DOI

10.1109/ECCTD.2009.5274936

Filename

5274936