A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier

A compact four-quadrant analog multiplier circuit using strong inversion saturated MOSFETs is presented. The circuit is formed by connecting simple 2-input "combiner" and "subtracter" cells in a novel topology. The proposed multiplier features low-voltage operation, very low quiescent power consumption, high-linearity and high operating frequency. In comparison with a previously reported multiplier circuit, simulated results using a 0.35-mum CMOS process show that, under the same static power consumption and supply voltage level of 1.2-V, the proposed circuit exhibits better linearity.