Title :
Improved Analytical I-V model for polygonal-shape enclosed layout transistors
Author :
López, P. ; Cabello, D. ; Hauer, H.
Author_Institution :
Dept. of Electron. & Comput. Sci., Univ. of Santiago de Compostela, Santiago de Compostela
Abstract :
An improved analytical I-V model accounting for the influence of short-channel effects on radiation-tolerant doughnut transistors is presented. The model is validated using TCAD simulation of the devices. The impact of this layout style on the driving capability of the devices is also analyzed confirming that it is seriously compromised in the case of large channel transistors which, together with an increase in the layout area discourages its use. However, for short-channel devices the driving capability is improved.
Keywords :
integrated circuit layout; semiconductor device models; technology CAD (electronics); transistors; TCAD simulation; analytical I-V model; polygonal-shape enclosed layout transistor; short-channel device; Analytical models; Annealing; CMOS technology; Charge measurement; Computer science; Current measurement; Semiconductor device modeling; Threshold voltage; Topology; Transistors;
Conference_Titel :
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4244-1341-6
Electronic_ISBN :
978-1-4244-1342-3
DOI :
10.1109/ECCTD.2007.4529706
