Techniques for implementation of at-speed testable, high performance, and low cost linear designs

Linear computations are most widely used type of ASIC computations. Due to their exceptional theoretical tractability and practical importance, numerous schemes for their implementation have been proposed. The canonical schemes have been widely studied and evaluated according to a number of important criteria, including the number of operations, number of bits, area, throughput and latency, and power metrics. However, until now the testability of linear systems was not studied. After we show that all the most widely used implementation structures require a significant testing related cost, we derive a new structure which is amenable for at-speed testing with no additional hardware overhead. Furthermore, the new structure provides a high throughput, low cost, and low power implementation for an arbitrary linear computation. The key technical novelties of the paper is a novel approach for use of transformations and coordinate use of transformations and scheduling for producing highly testable implementations