DocumentCode :
1569670
Title :
Technology mapping with crosstalk noise avoidance
Author :
Fan, Fang-Yu ; Chen, Hung-Ming ; Liu, I-Min
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2010
Firstpage :
319
Lastpage :
324
Abstract :
In today´s VLSI designs, crosstalk effects causing chips to fail or suffer from low yields have become one of the very essential design issues. In this paper, we attempt to reduce crosstalk noise in logic and physical synthesis stage, which is usually done in post-layout stage. We propose a technology mapping method that can reduce the crosstalk noise while meeting delay constraints. The algorithm employing a dynamic programming framework in the matching phase determines the routing of fanin nets for all the matches to estimate the track utilization in probability. These routings are stored as virtual routing maps to compute the crosstalk noise during the covering phase, which will select the crosstalk-minimal solutions satisfying the delay constraints rather than the delay-minimal ones. This problem is different from wire congestion-driven technology mapping and our experimental results are encouraging. We experiment on the benchmark circuits in 90nm process, the results show that, with 7% of area increase, our proposed approach is effective to improve the crosstalk by 28% on average, as compared to the conventional delay- and/or congestion-driven technology mapping. The overall result is better than the efforts done in post-layout stage, and has been validated by modern commercial EDA tools. In addition, this proposed approach can be applied in local technology remapping at post-placement/post-routing and ECO stages as well.
Keywords :
VLSI; circuit optimisation; crosstalk; dynamic programming; electromagnetic interference; integrated circuit noise; probability; VLSI designs; benchmark circuits; commercial EDA tools; crosstalk noise avoidance; dynamic programming; logic synthesis; physical synthesis; probability; track utilization; wire congestion-driven technology mapping; Circuits; Crosstalk; Delay; Dynamic programming; Heuristic algorithms; Logic programming; Phase estimation; Routing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
Type :
conf
DOI :
10.1109/ASPDAC.2010.5419876
Filename :
5419876
Link To Document :
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