DocumentCode
1569759
Title
A systolic RSA public key cryptosystem
Author
Chen, Po-Song ; Hwang, Shih-Arn ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
4
fYear
1996
Firstpage
408
Abstract
A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery´s algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance, A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock
Keywords
CMOS digital integrated circuits; VLSI; integrated circuit design; public key cryptography; systolic arrays; 24.3 Kbit/s; 50 MHz; 512 bit; CMOS VLSI chip; Montgomery´s algorithm; RSA public key cryptosystem; bit-level systolic array; encryption; Added delay; Algorithm design and analysis; Clocks; Iterative algorithms; Prototypes; Public key; Public key cryptography; Security; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541988
Filename
541988
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