A shared buffer memory switch for an ATM exchange

The authors propose a shared buffer memory switch in which output buffer memories are shared by all the switch output ports and are alloted to one particular output port as the occasion demands. This switch architecture can further improve the hardware-utilization efficiency of the memory switch by increasing the buffer memory usage rate. A discussion on switch traffic characteristics is provided and indicates that buffer sharing reduced the required memory size to less than 0.14 of that otherwise required for adequate switch size and estimates roughly the buffer size required for the switch. The large scale integration (LSI) count, for example, is about 15 chips for the main part of a 32×32 switch (150 Mb/s for each port) which can be mounted on one printed board. The switch is partitioned into a buffer memory LSI and a control LSI to make them flexible to change in ATM switch specifications