Title :
Features supporting system-level specification in HDLs
Author :
Narayan, Sanjiv ; Gajski, Daniel D.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems
Keywords :
formal specification; hardware description languages; multiprocessing systems; synchronisation; timing; CSP; Communicating Sequential Processes; HDL; HardwareC; SDL; SpecCharts; Statecharts; VHDL; concurrency; exception handling; hardware description languages; specification of embedded systems; synchronisation; synthesis tools; system-level specification; timing; Computer languages; Computer science; Embedded computing; Embedded system; Hardware design languages; High level synthesis; Process design; Specification languages; System-level design; Telecommunication computing;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410689
