A new linear readout circuit for a CMOS image sensor

This paper presents a high linearity, low area and low power column-parallel readout circuit with a modified 3 transistor active pixel sensor (3T-APS). Each column readout circuit consumes 43 uW power provided from the 3.3 V power supply and a small layout size of 10times300 um² is integrated in the 512 columns at one side of the pixel array. The modified pixel achieves the signal saturation voltage is the same as the standard APS structure, and the readout circuit linearity range is 99.9%. A high linearity 512times512 pixel CMOS image sensor with the proposed column-parallel readout circuit is designed based on 0.35 um 2P4M standard CMOS technology.