A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping

Author

Gu, Jie ; Eom, Hanyong ; Kim, Chris H.

Author_Institution

Minnesota Univ., Minneapolis

fYear

2007

Firstpage

126

Lastpage

127

Abstract

A low power switched decoupling capacitor circuit is proposed to suppress on-chip resonant supply noise. Compared to previous analog techniques, the proposed digital implementation achieves a 9X reduction in quiescent power with improved tolerance to PVT variation and tuning capability for optimal switching threshold. Measurements from a 0.13 mum test chip show an 11X boost in effective decap value and a 9.8 dB suppression in resonant supply noise by using the proposed circuit.

Keywords

CMOS digital integrated circuits; circuit resonance; circuit tuning; damping; integrated circuit noise; low-power electronics; switched capacitor networks; CMOS process; PVT variation; digital implementation; effective decap value; low power switched decoupling capacitor circuit; on-chip resonant supply noise suppression; on-chip supply resonance damping; optimal switching threshold; quiescent power reduction; size 0.13 mum; tolerance analysis; tuning capability; Circuit noise; Circuit optimization; Circuit testing; Damping; Noise measurement; Power capacitors; RLC circuits; Resonance; Switched capacitor circuits; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342684

Filename

4342684