High speed VLSI implementation of a finite field multiplier using redundant representation

Author

Namin, Ashkan Hosseinzadeh ; Leboeuf, Karl ; Muscedere, Roberto ; Wu, Huapeng ; Ahmadi, Majid

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada

fYear

2009

Firstpage

161

Lastpage

164

Abstract

A new VLSI implementation for a 197-bit finite field multiplier using redundant representation is presented. The proposed design uses a simple module designed in domino logic as the main building block for the multiplier. We have used .18 mum CMOS technology from TSMC for our design. The final multiplier design was successfully simulated at a clock rate of 1.82 GHz. The proposed multiplier is at least 190% more efficient compared to similar designs, considering the product of area and delay as a measure of performance. Large field size finite field multipliers which operate at high speeds, such as the proposed design, have applications in public key cryptography.

Keywords

CMOS integrated circuits; VLSI; high-speed techniques; logic design; multiplying circuits; public key cryptography; CMOS technology; domino logic design; finite field multiplier; high-speed VLSI implementation; public key cryptography; redundant representation; size 0.18 mum; storage capacity 197 bit; Area measurement; CMOS logic circuits; CMOS technology; Clocks; Delay; Galois fields; Logic design; Product design; Public key cryptography; Very large scale integration; Finite field arithmetic; domino logic; elliptic curve cryptography; multiplier; optimal normal basis type I; redundant representation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Conference_Location

Antalya

Print_ISBN

978-1-4244-3896-9

Electronic_ISBN

978-1-4244-3896-9

Type

conf

DOI

10.1109/ECCTD.2009.5274961

Filename

5274961