Title :
A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors
Author :
Fukuoka, Kazuki ; Ozawa, Osamu ; Mori, Ryo ; Igarashi, Yasuto ; Sasaki, Toshio ; Kuraishi, Takashi ; Yasu, Yosihiko ; Ishibashi, Koichiro
Author_Institution :
Renesas Technol. Corp., Tokyo
Abstract :
A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 μs and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique.
Keywords :
leakage currents; power semiconductor switches; leakage current; rush current control; ultra low-power single-chip mobile processors; wake-up time thick-gate-oxide power switch technique; Baseband; Current measurement; Equations; Leakage current; Logic gates; Parasitic capacitance; Resistors; Temperature; Variable structure systems; Voltage; PVT variation; leakage current reduction; rush current; thick-gate-oxide power switch;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-04-8
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342685
