Title :
Design and implementation of the cascode and cascade low noise amplifiers for 13 GHz
Author :
Wang, Yu-Lin ; Her, Man-Long
Author_Institution :
Ph. D. Program in Electr. & Commun. Eng., Feng-Chia Univ., Taichung, Taiwan
Abstract :
In this paper, we proposed two 13 GHz low noise amplifiers (LNAs) structure with TSMC 0.18 μm RF CMOS process. A cascode two-stage LNA achieves 9.9 dB of power gain (S21), 5.5 dB of the noise figure (NF), -32 dB of input return loss (S11), -5.2 dB of output return loss (S22), -8 dBm of the P1dB, and 6.66 mW of power consumption at 13 GHz, while consuming 3.7 mA by 1.8 V supply. The second LNA is a three-stage cascade LNA. Measured results show that the input return loss is -15.45 dB, the output return loss is -9.47 dB, the power gain is 9.34 dB, the isolation is -30.364 dB, the NF is 4.76 dB, the total power consumption is 26.64 mW, unconditional stability, the P1dB is -13 dBm, while consuming 14.8 mA by 1.8 V supply. The paper also discusses design considerations such as the effects of simulation, layout and circuit construction.
Keywords :
CMOS integrated circuits; low noise amplifiers; microwave amplifiers; microwave integrated circuits; TSMC RF CMOS process; cascade low noise amplifiers; cascode low noise amplifiers; cascode two-stage LNA; current 14.8 mA; current 3.7 mA; frequency 13 GHz; gain 9.34 dB; gain 9.9 dB; loss -15.45 dB; loss -32 dB; loss -5.2 dB; loss -9.47 dB; noise figure 4.76 dB; noise figure 5.5 dB; power 26.64 mW; power 6.66 mW; size 0.18 mum; three-stage cascade LNA; voltage 1.8 V; CMOS integrated circuits; RNA; Radio frequency; Receivers; Resistors; Cascade; Cascode; Low Noise Amplifier;
Conference_Titel :
Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC), 2011
Conference_Location :
Harbin
Print_ISBN :
978-1-4244-9792-8
DOI :
10.1109/CSQRWC.2011.6037028