DocumentCode
1570068
Title
A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers
Author
Ito, Hiroyuki ; Kimura, Makoto ; Okada, Kenichi ; Masu, Kazuya
Author_Institution
Tokyo Inst. of Technol., Yokohama
fYear
2007
Firstpage
136
Lastpage
137
Abstract
This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.
Keywords
integrated circuit interconnections; microprocessor chips; receivers; system buses; system-on-chip; transmitters; bit rate 8 Gbit/s; high-speed on-chip buses; low-latency multidrop on-chip transmission line interconnect; power 1.2 mW; power 7.1 mW; power dissipation; size 5 mm; two-way transceivers; Capacitance; Delay; Energy consumption; Impedance; Integrated circuit interconnections; Multicore processing; Peer to peer computing; Power transmission lines; Transceivers; Transmission lines; latency and signal integrity; on-chip bus;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-05-5
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342688
Filename
4342688
Link To Document