A small chip area 12-b 300MS/s Current Steering CMOS D/A converter based on a laminated-step layout technique

Author

Lee, Byungseung ; Kim, Byungill ; Lee, Juneseok ; Hwang, Sanghoon ; Song, Minkyu ; Wysocki, Tad

Author_Institution

Dept. of Semicond. Sci., Dongguk Univ., Seoul

fYear

2007

Firstpage

882

Lastpage

885

Abstract

A 12-b 300 MSPS Current-Steering DAC with 0.13 um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26 mm² even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12- b DAC performance. The measured results are within plusmn1 LSB for DNL. The measured SFDR is 70 dB under Nyquist output frequency with 50 mW power dissipation at 3.3 V power supply.

Keywords

CMOS integrated circuits; digital-analogue conversion; integrated circuit layout; CMOS technology; Nyquist output frequency; auto-averaging technique; current steering DAC; laminated-step layout technique; latched switching cell logic; power 50 mW; size 0.13 mum; voltage 3.3 V; word length 12 bit; Australia; CMOS logic circuits; CMOS process; CMOS technology; Decoding; Impedance; Logic circuits; Operational amplifiers; Routing; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on

Conference_Location

Seville

Print_ISBN

978-1-4244-1341-6

Electronic_ISBN

978-1-4244-1342-3

Type

conf

DOI

10.1109/ECCTD.2007.4529738

Filename

4529738