Timing Orthogonal Capacitance Multiplication Technique for PLL

Author

Wang, Ping-Ying ; Chen, Shang-Ping ; Chen, Paul

Author_Institution

MediaTek Inc., Hsin-Chu

fYear

2007

Firstpage

162

Lastpage

163

Abstract

In this paper, a timing orthogonal capacitance multiplication technique for PLL is proposed. Its advantages include: 1) Having a flexible, digitally programmable capacitance multiplication factor; 2) Not using op-amps, which reduces the noise contribution and is beneficial in aggressively scaled CMOS technology; and 3) Lowering cost through capacitance area reduction. At 800 MHz, a PLL using this technique consumes 3.3 mW from a 2.5 V supply and achieves <0.5% T_OSC RMS jitter. Its performance is comparable to the state-of-the-art while occupying only 125 mum times 100 mum, roughly 1/18 to 1/2 the area reported in recent publications.

Keywords

CMOS integrated circuits; UHF circuits; capacitance; flexible electronics; jitter; phase locked loops; PLL; RMS jitter; aggressively scaled CMOS technology; capacitance area reduction; cost reduction; digitally programmable capacitance multiplication factor; frequency 800 MHz; noise reduction; power 3.3 mW; size 100 mum; size 125 mum; timing orthogonal capacitance multiplication technique; voltage 2.5 V; Capacitance; Circuit noise; Clocks; Frequency; MOS capacitors; Phase detection; Phase locked loops; Phase noise; Sampling methods; Timing; PLL; capacitance multiplication; charge-pump;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342698

Filename

4342698