Title :
A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-μm CMOS
Author :
Hsieh, Hsieh-Hung ; Lu, Chung-Ting ; Lu, Liang-Hung
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
Implemented in a standard 0.18-mum CMOS process, a 0.5-V 1.9-GHz low-power phase-locked loop (PLL) is presented. Due to the use of the forward-body-bias technique, the threshold voltage of the MOSFETs is effectively reduced, making it possible to operate the PLL at an ultra-low supply voltage. In addition, various techniques for low-power and low-voltage operations are also adopted in the design of the building blocks. With a dc power consumption of 4.5 mW, the fabricated PLL measures in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100-kHz and 10-MHz frequency offset, respectively.
Keywords :
CMOS integrated circuits; MOSFET; UHF integrated circuits; low-power electronics; phase locked loops; CMOS process; MOSFET; PLL; frequency 1.9 GHz; metal-oxide-semiconductor field effect transistors; power phase-locked loop; size 0.18 mum; voltage 0.5 V; CMOS process; Energy consumption; Frequency measurement; MOSFETs; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Power measurement; Threshold voltage;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-04-8
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342699
